THERMAL · PHOTONIC · DOMESTIC

American carbon for American AI.

Three layers under the compute curve: per-die thermal personalization shipping today, fiber-photonic acceleration on the roadmap, and a carbon nanomaterial supply chain manufactured on U.S. soil.

Runs Cooler
−10°C
Lives 2× Longer
2.0× MTBF
Throughput
+5–12%
Drop-in
0 Rack Changes
TEAM AT A GLANCE
FULL TEAM →
JC
Jarom Christensen
CEO / Founder
Published inventor · 2× founder
DS
Dinesh Sastry
Capital Advisor
UC Berkeley EECS · Georgetown JD · Illuminant Capital
DC
Dave Christensen
Ops Advisor
CEO RMTG · VeriFone Global Service Repairs
CP
Calvin Passmore
Electrical Eng
Wavetronix · Space Dynamics Laboratory
MP
Matt Pennington
Control Systems Eng
Amazon Fulfillment automation
AS
Alexander Sorensen
Chemical Eng
Electrochemistry · published inventor

AI hit three walls.

Agentic AI demands roughly 100× more compute than the industry expected a year ago. The chips that meet that demand burn through their thermal budget before they hit their compute budget, move data through copper traces that can’t keep up with photonic-grade bandwidth, and ship through supply chains the U.S. doesn’t control.

Three walls. Three answers. One platform.

“The amount of computation we need at this point as a result of agentic AI, as a result of reasoning, is easily 100× more than we thought we needed this time last year.”
JENSEN HUANG, NVIDIA
THE THERMAL WALL
$25B+
Annual cooling-energy cost across global data centers. Active cooling dominates TCO; passive solutions don’t scale. Throttle is silent depreciation.
THE ELECTRON WALL
5–10×
Lower energy-per-bit for photonic interconnect vs. electrical SerDes (Ayar Labs, NVIDIA CPO). Copper hits a bandwidth and heat ceiling that fiber doesn’t.
THE SOVEREIGNTY WALL
>90%
Of leading-edge chip capacity sits outside U.S. borders. Carbon nanomaterials are an opportunity to onshore the next substrate layer from day one.

Three pillars. One carbon stack.

Each pillar attacks a different wall: thermal answers the cooling crisis, photonic answers the electron ceiling, and a domestic supply chain answers the sovereignty exposure. They share one feedstock and one manufacturing footprint.

PILLAR 01 · THERMAL MANAGEMENT

We don't cool the rack.
We cool the die.

The wedge product: GPU-Personalized Thermal. We image each die’s heat signature, lay down a proprietary thermal interface material exactly where it overheats, and bond targeted micro-fin arrays on top, recovering 8–15°C of junction headroom without changing the rack, the cold plate, or the workload.

1. FLIR Profiling
LWIR 8–14 µm. Identifying die-level hotspots.
2. Proprietary TIM
~30% reduction in thermal damage and reduction of cooling costs.
3. Micro-Fin Array
1–4 mm anodized. Targeted dissipation topology.
Why this wedge first: Compatible with all Direct Liquid Cooling (DLC) and immersion stacks. Zero rack-architecture change. Operates on a 6-month ship cycle. Tier A OEM design partner program opens Q3 2026.
STRATEGIC BENEFITS · PER-DIE PERSONALIZATION
Performance
+5–12%
Effective throughput. Recovered junction headroom translates to higher sustained clocks under TDP-bound inference at unchanged power draw.
Reliability
2.0×
Silicon MTBF. −10°C junction doubles mean time between failures; ~$5–10M annual depreciation reclaim per 10,000-GPU cluster.
Sustainability
−0.04
Stack-level PUE. Warmer permissible inlet temperatures lower chiller load; measurable lifecycle emissions reduction under standard LCA.

One service. One product.

Two commercial tracks running in parallel: a hands-on thermal personalization service for existing GPU fleets, and a product line of carbon components for advanced chip designs.

SERVICE
Thermal Management

For: Data centers · hyperscalers · OEM reference designs

Per-die FLIR profiling, proprietary TIM, and custom micro-fin arrays applied to each GPU exactly where it overheats. White-glove engagement; zero rack-architecture change.

You commit: Cluster access (or shipped silicon) and a named technical owner.

We commit: 5-day per-die turnaround at volume; 8–15°C junction drop; co-published operational data.

Engagement: NRE + per-unit, or managed-service contract.

PRODUCT
Carbon Components

For: Chip designers · OEMs · ASIC programs · photonic integrators

Custom CNT transistors, special-compound interconnects, photonic primitives, and integration support for leading-edge chips. Catalog parts for prototyping; custom design-ins for production.

You commit: Spec sheet, design intent, or BOM target.

We commit: Sample turnaround on catalog parts; NRE quote on bespoke designs; full integration support through qualification.

Engagement: Catalog pricing, custom NRE, or recurring supply.

PILLAR 02 · PHOTONIC COMPUTE

Light moves faster than electrons.

Copper interconnects are the next thermal and bandwidth bottleneck in AI accelerators. Every chip-to-chip hop costs energy as heat, and the wires can’t move data fast enough to keep tensor cores fed. Photonic compute swaps electrons for photons in the dense data paths. Same silicon, fundamentally different physics.

Our development track focuses on three carbon-enabled photonic primitives: low-loss optical fiber and waveguides, carbon-nanotube photodetectors, and chip-edge optical interfaces designed to drop into existing co-packaged-optics roadmaps from NVIDIA, Broadcom, and Marvell.

Maturity: early R&D. Carbon nanomaterials demonstrate measured advantages in photonic switching speed and on-chip absorption versus conventional photonic platforms. Productization follows our thermal revenue.

BANDWIDTH
10×+
Per-lane bandwidth of photonic vs. high-speed copper SerDes. Carbon fiber preserves signal across longer reaches without retiming.
ENERGY / BIT
<1 pJ
Target energy-per-bit for co-packaged photonic interconnect, an order of magnitude below electrical equivalents at scale.
DROP-IN
CPO
Designed against the co-packaged-optics standard so the photonic stack lands inside reference architectures, not next to them.
PILLAR 03 · DOMESTIC PIPELINE

Reshored from the carbon up.

Carbon is one of the rare advanced-compute substrates where the United States can build a supply chain from scratch rather than negotiate with overseas incumbents. Every step of our pipeline runs on American soil, from raw material sourcing through manufacturing to final integration. The domestic stack is the asset; the products are what it enables.

01 · SOURCING
U.S.-based supply
Every raw input comes from American suppliers. No dependence on supply chains the United States doesn’t control.
02 · MANUFACTURING
American operations
Production runs at U.S. facilities, in-house and through American manufacturing partners. The capability lives here, not in someone else’s foundry.
03 · INTEGRATION
Domestic assembly
Finished components and assemblies are built in the U.S. for U.S. customers, with the workflows and clearances required for defense and federal use.
CHIPS ACT
Advanced Manufacturing
Eligible for advanced manufacturing incentives, R&D tax credits, and fab-readiness funding under the CHIPS and Science Act.
DARPA
Defense Electronics
Aligned with active programs in advanced materials, edge AI, and defense electronics. Direct technical fit for ongoing solicitations.
SBIR / STTR
DoD · NSF · NIH · DOE
Multi-agency eligibility across the federal R&D portfolio. Non-dilutive support running in parallel with commercial deployment.
The strategic asset: a domestic carbon manufacturing base, ready for defense and CHIPS-aligned procurement, that doesn’t currently exist in the United States. We are building it as the foundation for everything we ship.

$64B market. We start at the edge.

TAM: $64BAI accelerators + thermal mgmt, 25–35% CAGR (2030)
SAM: $8.5BEdge AI + thermal where CNT dominates
SOM: $120M3-year achievable, 3–5 pilots in Year 1
STATE OF THE COMPANY
Stage
Pilot Prep
Pipeline
30 Active
Gov Programs
3 in Flight
Shipping
Per-Die Thermal

A domestic buyer ladder.

Every customer tier starts U.S.-based and DoD-eligible. We climb from data-center thermal contracts into hyperscaler co-development, then into OEM reference designs, with photonic components opening a parallel design-in track as the technology matures.

Tier 1 · Now
U.S. data center operators: thermal personalization contracts on existing GPU fleets. Custom TIM + micro-fin application.
~7 active
Tier 2 · 12 mo
Hyperscalers: Meta, Microsoft, Google, AWS. Instrumented thermal pilots and early photonic co-development on U.S. clusters.
~12 seeded
Tier 3 · 24 mo
U.S. OEMs: Dell, HPE, Supermicro, Lenovo. Reference-design integration of thermal stack; first photonic component qualification.
~11 active
Tier 4 · Defense / Gov
DoD primes, national labs, and federal R&D agencies via SBIR/STTR and DARPA. Non-dilutive pull through the same domestic stack.
Parallel track

Team

Operators and inventors who’ve shipped at Amazon, VeriFone, Space Dynamics Laboratory, and Wavetronix, paired with capital strategists who’ve raised across the U.S., U.K., India, and Asia-Pacific.

Recruiting Now

Actively recruiting 3 advisor profiles: published CNT physicist, retired semiconductor industry executive, and DARPA / government-contracts veteran.

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